时 间：2025年4月9日，9:30-10:30（GMT +08:00北京时间）
地 点：哈工大活动中心320会议室
主讲人：瑞士洛桑联邦理工学院David Atienza教授（IEEE FELLOW、ACM FELLOW）
邀请人：哈工大计算学部主任 王忠杰教授
主持人：哈工大计算学部人工智能学院执行院长 张伟男教授
题目：面向低功耗与个性化可穿戴设备的以加速器为中心边缘AI架构
Title: Accelerator-Centric Edge AI Architectures for Low-Power and Personalized Wearables
摘要:
如今，边缘AI计算正涉足多个领域，一系列互补的新兴方法已成为设计信息物理系统（CPS）和可穿戴系统的新型以加速器为中心架构的主要途径。第一种方法基于在计算系统中集成增强的通用组件（例如在常规内存块中添加计算能力，即内存计算），作为边缘AI系统微架构的一部分，该系统包含经过验证的开放硬件组件（处理器、内存及外设）。第二种方法则通过将新型加速器模块作为目标应用领域的独立协处理模块集成到最终边缘AI架构中，从而构建特定领域的异构片上系统（SoC）平台。
本次讲座中，David Atienza教授将探讨这两种方法的优缺点，重点阐述如何基于X-HEEP开源硬件SoC架构模板的最新研究将两者结合。具体而言，将展示如何集成不同类型的加速器家族（例如内存加速与近内存加速、脉动阵列与粗粒度可重构阵列（CGRA）），以设计面向个性化医疗的新一代多参数边缘AI可穿戴设备。
个人简介:
David Atienza现任瑞士洛桑联邦理工学院（EPFL）电气与计算机工程教授，兼任嵌入式系统实验室（ESL）主任，并于2024-2028年担任EPFL负责研究中心与平台的协理副校长。他的研究方向包括面向低功耗信息物理系统（CPS）和高能效计算服务器的多处理器片上系统（MPSoC）设计方法学。近期工作涵盖针对边缘AI系统的2.5D/3D功耗-热感知MPSoC架构设计，以及在物联网（IoT）背景下通过硬件/软件协同设计与基于AI的多层级优化实现可持续计算。
David Atienza教授在上述领域合著了450余篇论文、1部专著，并拥有14项专利。他曾获多项荣誉与奖项，包括2024年IEEE/ACM硬件/软件协同设计会议（CODES-ISSS）持久影响力奖（表彰过去15年最具影响力的论文）、2020年ICCAD十年回顾最具影响力论文奖、2018年设计自动化会议（DAC）40岁以下创新者奖，以及IEEE CEDA和ACM SIGDA在EDA工具与系统研究领域的早期职业成就奖。他是IEEE和ACM会士，并于2022至2024年担任欧洲设计自动化协会（EDAA）主席，目前担任《IEEE计算机辅助设计汇刊》（T-CAD）和《ACM Computing Surveys》的主编。
Title: Accelerator-Centric Edge AI Architectures for Low-Power and Personalized Wearables
Abstract:
Edge AI computing is targeting multiple domains nowadays, and a new set of complementary approaches have emerged as main avenues for designing novel accelerator-centric architectures for Cyber-Physical Systems (CPS) and wearable systems. The first approach is based on integrating enhanced general-purpose components in computing systems (such as adding computing capabilities in regular memory blocks, also called in-memory computing) as part of the micro-architecture of an edge AI system that comprises validated open hardware components (processors, memories, and peripherals). The second approach includes new accelerator modules inside the final edge AI architectures as a separate co-processing module of the target application domain, enabling new domain-specific heterogeneous system-on-chip (SoC) platforms. In this lecture, Prof. Atienza will cover the pros and cons of these two approaches, focusing on how to combine both based on recent research done within the X-HEEP open-hardware SoC architectural template. In particular, it will be shown how to integrate different families of accelerators, such as in-memory vs. near-memory acceleration or systolic arrays vs. Coarse-grained reconfigurable arrays (CGRA) to design the next generation of multi-parametric edge AI wearables targeting personalized healthcare.
Biography:
David Atienza is a professor of Electrical and Computer Engineering, heads the Embedded Systems Laboratory (ESL) and is the Associate Vice President of Research Centers and Plaforms for the period 2024-2028 at EPFL, Switzerland. His research interests include system-level design methodologies for multi-processor system-on-chip (MPSoC) targeting low-power Cyber-Physical Systems (CPS) and energy-efficient computing servers. His latest works include new 2.5D/3D power/thermal-aware design and architectures for MPSoCs targeting edge AI systems, as well as HW/SW co-design and AI-based multi-level optimization for sustainable computing in the Internet of Things (IoT) context.
Prof. David Atienza has co-authored over 450 papers, one book, and 14 patents in these previous areas. He has also received multiple recognitions and awards, among them the IEEE/ACM HW/SW Co-Design Conference (CODES-ISSS) 2024 Test-of-Time Award for the most influential paper in the last 15 years, the ICCAD 10-Year Retrospective Most Influential Paper Award in 2020, the Design Automation Conference (DAC) Under-40 Innovators Award in 2018, and IEEE CEDA and ACM SIGDA Early Career Awards on EDA tools and systems research. He is a Fellow of IEEE, Fellow of ACM, and was the Chair of the European Design Automation Association (EDAA) since 2022 until 2024. He is currently the Editor-in-Chief of IEEE Trans. on CAD (T-CAD) and ACM Computing Surveys.
